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Philips Semiconductors
PCF85103C-2
256 × 8-bit CMOS EEPROM with I 2 C-bus interface
11. I 2 C-bus characteristics
Table 8: I 2 C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to V IL and V IH
with an input voltage swing from V SS to V DD ; see Figure 9 .
Symbol
f SCL
t BUF
Parameter
clock frequency
bus free time between a STOP and
Conditions
Min
0
4.7
Max
100
?
Unit
kHz
μ s
START condition
t HD;STA
START condition hold time after
4.0
?
μ s
which ?rst clock pulse is generated
t LOW
t HIGH
LOW level clock period
HIGH level clock period
4.7
4.0
?
?
μ s
μ s
t SU;STA
set-up time for START condition
repeated start
4.7
?
μ s
t HD;DAT
data hold time
for bus compatible masters
5
?
μ s
for bus devices
[1]
0
?
ns
t SU;DAT
t r
t f
t SU;STO
data set-up time
SDA and SCL rise time
SDA and SCL fall time
set-up time for STOP condition
250
?
?
4.0
?
1
300
?
ns
μ s
ns
μ s
[1]
The hold time required (not greater than 300 ns) to bridge the unde?ned region of the falling edge of SCL must be internally provided by
a transmitter.
SDA
t BUF
t LOW
tf
t HD;STA
SCL
P
S
S
P
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
t SU;STA
MBA705
t SU;STO
P = STOP condition; S = START condition.
Fig 9. Timing requirements for the I 2 C-bus.
9397 750 14218
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 04 — 22 October 2004
11 of 20
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